| Input Name | Bit Width | Number of Inputs | Input of | Description |
| Phonon Inputs from ADC | 16 bits/channel | 12 channels | Downsample Filter | The 12 phonon inputs are digitized in an ADC on the DCRC at a rate of 625 kHz. We note that this is done on 3 ADC chips with 4 ADC's per chip. |
| Charge Inputs from ADC | 16 bits/channels | 4 channels | Downsample Filter | The 4 phonon inputs are digitized in an ADC on the DCRC at a rate of 2.5 MHz. We note that this is done on 2 ADC chips with 2 ADC's per chip. |
| Input Name | Bit Width | Number of Registers | Input of which module(s) | Description |
| Linear Combination Coefficients | 8 bits/channel | 16 channels/submodule × 4 submodules | Linear Combination |
These are the coefficients used in the LC module to compute the linear combination of the set of phonon and charge inputs. They have two distinct uses. The first use is to select only a subset of the 16 input channels for use in one of the trigger waveforms. For example, the coefficients for all side 1 phonon channels might be set to 1 while all other coefficients are set to 0, in order to create a side 1 only trigger. The second use is to include channel-relative calibrations. For example, if one phonon channel is known to have a response 20% larger than the other phonon channels, then the corresponding coefficient might be set 20% lower than the other phonon coefficients. The default is to set the charge coefficients to 0 and the phonon coefficients to 1. This produces a phonon-only trigger that uses both sides of the detector. |
| Linear Combination Pre-Truncation Shift | 1 integer (range 0 to 28) / submodule | 1 value / submodule × 4 submodules | Linear Combination |
The LC module produces outputs that are 46 bits wide, but the FIR module expects inputs that are only 18 bits wide. The 46-bit values are truncated to 18 bits, but before truncation they are shifted left by a configurable number of bits (that is, multiplied by a configurable power of 2). If the shift would cause the value to overflow or underflow, then it is set to the maximum or minimum possible 46-bit value, respectively. In the shift, the least-significant bits are filled with zeros. After the shift, the 18 most-significant bits are kept, and the 28 least-significant bits are discarded. |
| Finite Impulse Response Coefficients | 16 bits/coefficient | 1024 coefficients/submodule × 4 submodules (Note: This is implemented as only three addressable registers: one address register, one module-select register, and one data port register) | Finite Impulse Response | These coefficients define the response of the Finite Impulse Response Filter used in the L1 trigger. |
| Finite Impulse Response Pre-Truncation Shift | 1 integer (range 0 to 28) / submodule | 1 value / submodule × 4 submodules | Finite Impulse Response |
The FIR module produces outputs that are 44 bits wide, but the ThL module expects inputs that are only 16 bits wide. The 44-bit values are truncated to 16 bits, but before truncation they are shifted left by a configurable number of bits (that is, multiplied by a configurable power of 2). If the shift would cause the value to overflow or underflow, then it is set to the maximum or minimum possible 44-bit value, respectively. In the shift, the least-significant bits are filled with zeros. After the shift, the 16 most-significant bits are kept, and the 28 least-significant bits are discarded. |
| Activation Thresholds | 16 bits/threshold | 1 threshold/submodule × 8 submodules | Threshold Logic | The input trigger waveform values are compared to these thresholds to make the discriminator decisions, and set the "threshold logic bits" (which is 1 when the trigger waveform goes above this threshold). The discriminator decision and threshold logic bits are used in the Peak Search module as part of the peak search window and trigger primitive determination. |
| Deactivation Thresholds | 16 bits/threshold | 1 threshold/submodule × 8 submodules | Threshold Logic | The input trigger waveform values are compared to these thresholds to make the discriminator decisions, and set the "threshold logic bits" (which is 0 when the trigger waveform goes below this threshold). The discriminator decision and threshold logic bits are used in the Peak Search module as part of the peak search window and trigger primitive determination. |
| Threshold Logic Selectors | 2 bits/selector | 1 selector/submodule × 8 submodules | Threshold Logic and Peak Search |
These selectors are used to choose which of the 4 trigger waveform channels (FIR outputs) will be compared to the corresponding thresholds. The Peak Search module looks at the Threshold Logic Selectors to find which of the threshold logic bits to use to define the peak search window. |
| Max window length $t_\text{max}$ | 16 bits/register | 1 register/submodule × 4 submodules | Peak Search | The length of the measured peak search window is compared to this length. If it is larger than this length, it identifies the pulse as being a saturated pulse. |
| Saturated-pulse timestamp offset $\Delta t_\text{sat}$ | 16 bits/register | 1 register/submodule × 4 submodules | Peak Search | For pulses identified as saturated pulses, this offset is used in addition to the peak search window start to calculate the reported peak timestamp. |
| Require Masks | 16 bits/mask | 1 mask/output trigger bit × 8 output trigger bits | Trigger Logic | These masks are used to check each incoming trigger word to tell which bits of the trigger word are required to be 1. |
| Veto Masks | 16 bits/mask | 1 mask/output trigger bit × 8 output trigger bits | Trigger Logic | These masks are used to check each incoming trigger word to tell which bits of the trigger word are required to be 0. |
| Trigger Logic Selectors | 2 bits/selector | 1 selector/output trigger bit × 8 output trigger bits | Trigger Logic | These two bits are used to choose which Peak Search module results will be used for each of the 8 trigger bits produced by the Trigger Logic module (described in the TrL page). |
| Prescale Probabilities | 16 bits/probability | 1 probability/output trigger bit × 8 output trigger bits | Trigger Logic | Sets the probability that triggers will be rejected probabilistically. Setting this to 0xFFFF will mean no triggers get rejected. Setting this to 0x0000 will mean triggers are only accepted at a rate of 1 out of every 65536. That is, the accept rate is this register's value plus one, divided by 65536. |
| Enable Bits | 1 bit each | 1 enable bit/output trigger bit × 8 output trigger bits | Trigger Logic | This bit is used to turn individual bits (8 bits total) in the Trigger Logic module's output on or off. Setting this register to 1 allows the Trigger Logic module to set the corresponding bit normally. Setting this register to 0 forces the corresponding bit in the trigger word output to always be 0. |
| Random Trigger Threshold | 32 bits | 1 threshold | Random Trigger | A random trigger is inserted into the L1 FIFO when a random number, generated in the module, goes above this threshold. |
| LEMO trigger configuration | 1 bit/value | 2 values | External Triggers and Vetos |
The ETV module can be configured to trigger on rising LEMO edges, falling LEMO edges, both, or neither. |
| LEMO veto configuration | 1 bit/value | 2 values | External Triggers and Vetos |
The ETV module can be configured to veto when the LEMO input is high, low, or neither. Note that configuring it to veto in both conditions is considered an error as this would prevent all triggering. |
| SDU message response | 2 bits/value | 216 values | External Triggers and Vetos |
The response of the ETV module to an incoming SDU message can be configured. The possible responses are "neither trigger nor veto", "trigger", "veto", and "trigger and veto". Because each SDU message is 16 bits, there are 216 possible messages. The response to each message can be configured independently. |
| Trigger FIFO pop | 0 bits | 1 pop | L1 FIFO |
The trigger FIFO "pops" or discards the current head and moves on the next entry when any value is written to the address of this register. Note that the value written to this address is irrelevant and ignored, which is why it is marked as "0 bits". Only the fact that a write request occurred, and no actual written data, is passed to the L1 FIFO module. This makes it a control input but not a configuration input. |
| Veto FIFO pop | 0 bits | 1 pop | L1 FIFO |
The veto FIFO "pops" or discards the current head and moves on the next entry when any value is written to the address of this register. As in the Trigger FIFO pop, note that the value written to this address is irrelevant and ignored, which is why it is marked as "0 bits". Only the fact that a write request occurred, and no actual written data, is passed to the L1 FIFO module. This makes it a control input but not a configuration input. |
| Input Name | Bit Width | Number of Inputs | Input of | Description |
| Current Timestamp | 32 bits/timestamp | Not an addressable register -- these 32 bits are a counter internal to the FPGA which the trigger firmware can use. | Peak Search, Random Trigger, External Triggers and Vetos and L1 FIFO |
At the start of a data-taking series, this counter is set to 0. Then, every time a phonon ADC sample is recorded (every 625 kHz), the counter is incremented by one. The Peak Search, Random Trigger and External Trigger and Veto modules use this counter to determine the timestamp that should be recorded into the L1 Trigger FIFO for each trigger. The L2 trigger will use this timestamp to decide which portions of the data to read out from the DCRC. The L1 FIFO module uses this counter to determine the timestamp that should be recorded into the veto FIFO, and help to track the live-time and dead-time. |
| LEMO input | 1 bit | External Triggers and Vetos | The LEMO input is a logic-level signal that may optionally be input to the DCRC. Its use is intended principally for test facilities. The trigger may be configured to trigger or veto based on the LEMO signal. | |
| SDU messages | 16 bits per message | External Triggers and Vetos | The Signal Distribution Unit (SDU) can be used to send 16 bit messages to the DCRCs. Its primary purpose is to synchronize data-taking among all the DCRCs, but it can also be used to command triggers or veto periods. The trigger may be configured to trigger or veto based on each possible SDU message. |
