Linear Combination (LC)

• The input contains the following information:
  • phonon channels 1-12
  • charge channels 1-4
• The input is formatted as a 16-channel packetized Avalon-ST stream.
  • The input stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 34 bit wide data signal (which is used to carry the 16 inputs in serial)
    • 4 bit wide channel-number signal (to specify which of the 16 channels each datum belongs to)
    • 1 bit wide valid signal
    • 1 bit wide start-of-packet signal
    • 1 bit wide end-of-packet signal
  • Packets will be received at a rate of 39.0625 kHz.
  • Note that each phonon channel and each charge channel is carried on its own Avalon-ST channel, and we assume an order in this description of all the phonon channels first (0-11) and then the charge channels (12-15). That is, when receiving a sample from phonon channel 1, the Avalon-ST channel number bits will be set to 0000. When receiving a sample from phonon channel 12, the Avalon-ST channel number bits will be set by the Synchronizer module to 1011. When receiving a sample from charge channel 1, the Avalon-ST channel number bits will be set to 1100. When receiving a sample from charge channel 4, the Avalon-ST channel number bits will be set to 1111. That is, phonon channels 1-12 are received on Avalon-ST channels 0-11 respectively, and charge channels 1-4 are received on Avalon-ST channels 12-15 respectively.
  • Since the input carries multiple channels, exactly one datum from each constituent channel will be received in series as a single Avalon-ST packet.
  • The charge samples use all 34 data bits, but the phonon samples use only 26, so they are zero-padded. For phonon samples, the 8 least-significant data bits are set to all zeros, and the 26 most-significant data bits carry the phonon sample data.

• Linear Combination Coefficients $w_{i}$: 8 bits/channel, 16 channels/submodule, 4 submodules
• Linear Combination Pre-Truncation Shift: 1 integer (range 0 to 28) /submodule, 4 submodules
• 100 MHz clock input
• 1 reset input

Note that the design for this module is very flexible. We can set the Linear Combination Coefficients $w_{i}$ differently for different running types. For example, since the default running type is to ignore the charge inputs, the default Linear Combination Coefficients $w_{i}$ ($i$ = 12, 13, 14 and 15) for charge will be set to zero.

The coefficients $w_{i}$ are set during initialization¹ at the start of running and are expected to remain the same after that, but they can be changed at any time if needed.

• The output contains the following information:
  • Four linear combinations (one from each submodule) of the 16 inputs (truncated to 18 bits each, see detailed description below)
• The output is formatted as a 4-channel packetized Avalon-ST stream.
  • The output stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 18 bit wide data signal (which is used to carry the 4 outputs in serial)
    • 2 bit wide channel-number signal (to specify which of the 4 channels each datum belongs to)
    • 1 bit wide valid signal
    • 1 bit wide start-of-packet signal
    • 1 bit wide end-of-packet signal
    • 2 bit wide error signal (unused, so always set to 00)
  • Packets will be sent at a rate of 39.0625 kHz, in lockstep with the input packets, with some latency which we will measure during testing of this module.
  • Note that the outputs from all 4 submodules are collected into a single 4-channel stream before they are passed to the FIR module. The 4 submodule outputs are sent as a single packet to the FIR module, with each FIR submodule pulling its assigned data from the stream.

The module detects and reports several possible erroneous conditions via a register read. The value read out consists of 16 bits; the most-significant bits are unused.

• Bit 0: Received data outside of a packet
• Bit 1: Received start-of-packet signal during a packet
• Bit 2: Received end-of-packet signal outside of a packet
• Bit 3: Duplicated channel in a packet
• Bit 4: Missing channel in a packet
• Bit 5: Illegal channel number in input
• Bit 6: Read or write to invalid register address
• Bit 7: Invalid value written to register
• Bit 8: Input packets arrived too close together
• Bit 9: Accumulator over/underflow

Each submodule computes a linear combination of its 16 inputs $\text{input}_i[n]$ and outputs it as a single output $\text{output}[n]$. \[\text{output}[n] = \sum_{i=0}^{15} w_{i} \cdot \text{input}_i[n]\text{, where}\]

• $\text{input}_i[n]$ is the \(n\)th input received by this module on the \(i\)th channel.
• $\text{output}[n]$ is the \(n\)th output produced by this module. It is calculated from the \(n\)th input received by this module, $\text{input}_i[n]$.
• $i= 0, 1, ..., 15$ indexes the 16 input channels: 12 phonon and 4 charge channels (as noted above).
• $w_{i}$ is the coefficient multiplying the \(i\)th channel.

1. Wait for an input packet to arrive from the Synchronizer module
2. When input data is arriving ("valid" input bit is set on a rising clock edge, start-of-packet bit is set on the first clock cycle of the packet and end-of-packet bit is set on the last clock cycle of the packet), do the following:
   • Read the channel number bits (0000-1111) to determine which input we got on this clock cycle. Channels 0000-1011 are phonon channels 1-12, and channels 1100-1111 are charge channels 1-4.
   • Set one of the inputs of a hardware multiply-accumulate block to the weight $w_i$ corresponding to this input, where $i$ is the channel number
   • Read the data bits and set the other input of the hardware multiply-accumulate block to the data $\text{input}_i[n]$.
3. When the input packet transfer is complete (end-of-packet bit set on the previous clock cycle), then compute the output:
   1. The output of the hardware multiply-accumulate block now contains the sum of the 16 weighted inputs.
   2. Left-shift the sum by a configurable number of places, clipping over- and under-flows to the maximum and minimum values respectively.
   3. Truncate the left-shifted sum from 46 bits to 18 bits, keeping the 18 most-significant bits.
   4. The truncated sum is $\text{output}[n]$.
   5. Reset the hardware multiply-accumulate block
4. The output of each submodule is sent, along with the outputs from the other three submodules, in a single 4-channel Avalon-ST packet, where we send the output for LC1 first, then LC2, LC3, and LC4 in sequence. On 5 consecutive clock cycles, perform the following operations:
   1. Set the 18 data bits to the output of LC module 1. Concurrently, set the 2 channel-number bits to 00, set the valid bit, and set the start-of-packet bit.
   2. Set the 18 data bits to the output of LC module 2. Concurrently, set the 2 channel-number bits to 01, and unset the start-of-packet bit.
   3. Set the 18 data bits to the output of LC module 3. Concurrently, set the 2 channel-number bits to 10.
   4. Set the 18 data bits to the output of LC module 4. Concurrently, set the 2 channel-number bits to 11, and set the end-of-packet bit.
   5. Unset the valid bit, and unset the end-of-packet bit.

Reset Signal:

• Set all the coefficients to zero
• Reset the subsystem that monitors the input packets and checks them for errors
• Reset the hardware multiply-accumulate blocks
• Set all the error bits to zero

• Go back to Step 1 of the detailed description.

• ¹ Since a very large number of settings on the DCRC (both in the trigger firmware and in the rest of the DCRC firmware) have to be correct in order to take data, we expect that MIDAS will write appropriate values into all the relevant registers at a time when we are not taking data. Those values will then be mostly unchanged during data taking. Doing this before the start of data taking is what we mean by "initialization". The full list of configuration parameters for the L1 trigger firmware is available on the inputs page.

• See here for the overall testing plan.
• See here for the testing plan for this module.