Design and Implementation of the CDMS Level 1 trigger

The diagram below describes the design of the L1 trigger firmware, as implemented in git. Each block in the diagram is a link to a page with more details about the design and implementation.

• This design, and the details of the processing and data passing, is based on its implementation in the FPGA on the DCRC (Altera Cyclone IV). There are clock and reset inputs (which we didn't put on the diagram) to each block, and each clock input is at 100MHz clock rate. Most blocks also have an error output, which is also not shown on the diagram but is described on each block's page.
• Quick functionality description: the phonon inputs come in from the ADCs at a rate of 625 kHz and the charge inputs come in at a rate of 2.5MHz. After downsampling (implemented in module Down Sample Filter), they come out at a rate of 39.0625 kHz and are synchronised and are pushed through the trigger (implemented in modules Synchronizer, Linear Combination (LC), FIR, Threshold Logic (ThL), and Peak Search (PS)) in lockstep to compute the trigger primitives. The output of PS is asynchronous as it only outputs if it finds a trigger primitive. The Trigger Logic module computes the final L1 trigger decision, and outputs the result to the L1 FIFO. The L1 FIFO will write the trigger primitives into the FIFO or discard them, based on the L1 trigger decision.
• Each dashed box indicates a module. The small boxes (submodules) inside the same large dashed box have the same functions, and are implemented with identical code. Since the inputs to each sub-module may vary the outputs may vary. In many cases, as indicated in the figure below, the outputs of the submodules are combined to create a single output from the module.
• In addition to the design, we have created a full testing suite which can be found here. We tested each module in isolation in simulation (modelsim), then tested each module in isolation on our tester board. Then, we tested the entire trigger (all the modules together) in simulation and again in hardware on the tester board. Lastly, we will test the entire trigger on the DCRC. (Note that we will not do the tests of individual modules on the DCRC.)
• This trigger firmware design will work with both iZIP and HV detectors. The only change is that the unused ADC inputs on HV DCRCs will need to be hooked up to dummy data.
• This design uses only a fraction of the FPGA's resources. The trigger uses 12 of the FPGA's 200 multiplier blocks (8 in the LC module and 4 in the FIR module), and 55 of the FPGA's 305 memory blocks (dominated by 23 in the DF module and 16 in the FIR module).
• Throughout the design, we use the "signed" and "unsigned" numeric types from the IEEE "numeric_std" library. This gives us two's-complement integers with a consistent endianness.