Finite Impulse Response (FIR)

• The input contains the following information:
  • Linear combinations 1-4
• The input is formatted as a 4-channel packetized Avalon-ST stream.
  • The input stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 18 bit wide data signal (which is used to carry the 4 inputs in serial)
    • 2 bit wide channel-number signal (to specify which of the 4 channels each datum belongs to)
    • 1 bit wide valid signal
    • 1 bit wide start-of-packet signal
    • 1 bit wide end-of-packet signal
    • 2 bit wide error signal (unused, so always set to 00)
  • Packets will be received at a rate of 39.0625 kHz.
  • Note that each of the 4 linear combinations is carried on its own Avalon-ST channel. That is, when receiving a sample from LC 1, the Avalon-ST channel number bits will be set to 00. When receiving a sample from LC 2, the channel number bits will be set to 01, etc. That is, samples from LC 1-4 are received on Avalon-ST channels 0-3, respectively.
  • Each packet will consist of exactly 4 data, one from each of the 4 LC submodules. Each FIR submodule will use exactly one datum, the one from the corresponding LC submodule.

• Finite Impulse Response Coefficients $b_{i}$: 16 bits/coefficient, 1024 coefficients/submodule, 4 submodules
• Finite Impulse Response Pre-Truncation Shift: 1 integer (range 0 to 28) / submodule, 4 submodules
• 100 MHz clock input
• 1 reset input

Note that the Finite Impulse Response Coefficients are set during initialization¹ at the start of running and are expected to remain the same after that, but they can be changed at any time if needed.

• The output contains the following information:
  • Trigger waveforms 1-4
• The output is formatted as a 4-channel packetized Avalon-ST stream.
  • The output stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 16 bit wide data signal (which is used to carry the 4 trigger waveform outputs in serial)
    • 2 bit wide channel-number signal (to specify which of the 4 channels each datum belongs to)
    • 1 bit wide valid signal
    • 1 bit wide start-of-packet signal
    • 1 bit wide end-of-packet signal
    • 2 bit wide error signal (which is ignored)
  • Packets will be sent at a rate of 39.0625 kHz, in lockstep with the input packets, with some latency which we will measure during testing of this module.
  • Note that the outputs from all 4 submodules are collected into a single 4-channel stream before they are passed to the Threshold Logic (ThL) module. The 4 submodule outputs are sent as a single packet to the ThL module, with each ThL submodule pulling its assigned data from the stream.

The module detects and reports several possible erroneous conditions via a register read. The value read out consists of 16 bits; the most-significant bits are unused.

• Bit 0: Received data outside of a packet
• Bit 1: Received start-of-packet signal during a packet
• Bit 2: Received end-of-packet signal outside of a packet
• Bit 3: Duplicated channel in a packet
• Bit 4: Missing channel in a packet
• Bit 5: Illegal channel number in input
• Bit 6: Read or write to invalid register address
• Bit 7: Invalid value written to register
• Bit 8: Input packets arrived too close together
• Bit 9: Output packets colliding
• Bit 10: Accumulator over/underflow

For an FIR filter, each value of the output sequence is a weighted sum of the most recent 1024 input values in time: \begin{aligned} \text{output}[n] & = b_{0} \cdot \text{input}[n] + b_{1} \cdot \text{input}[n-1] + \cdots + b_{1023} \cdot \text{input}[n-1023] \\ & = \sum_{i=0}^{1023} b_{i} \cdot \text{input}[n-i]\text{, where} \end{aligned}

• $i= 0, 1, 2, \cdots, 1023$ (indexes the most recent 1024 inputs from Linear Combination module)
• $b_{i}$ is the $i$'th coefficient
• $\text{input}[n-i]$ is the $i$'th most recent input in time stored in internal registers (e.g., $ \text{input}[n] $ is the most recent input, $ \text{input}[n-1] $ is the previous input)

Step-by-step:

1. Wait for an input packet to arrive from the LC modules
2. Dispatch each of the input data to the appropriate FIR submodule: input from LC 1 goes to FIR 1, LC 2 to FIR 2, etc.
3. Store the 1024 most recent input values to each submodule -- when each input is received, discard the oldest stored input and store the new input.
4. Multiply each of the 1024 stored input values $\text{input}[n-i]$ by the corresponding coefficient $b_{i}$
5. Sum the 1024 weighted values $b_{i} \cdot \text{input}[n-i]$
6. Send the sum as an $\text{output}[n]$
7. Left-shift the sum by a configurable number of places, clipping over- and under-flows the maximum and minimum values, respectively.
Truncate the left-shifted sum from 44 bits to 16 bits, keeping the 16 most-significant bits.
8. Return to step 1
9. The output of each FIR module is sent with the other three FIR modules in a single Avalon-ST packet, where we send the outputs for FIR1 first, then FIR2, FIR3 and FIR4 respectively using the same operations as described in the step 4 of LC module here.

Reset Signal:

• Reset the subsystem monitoring the input packets and checking for errors
• Reset the hardware multiply-accumulate blocks that perform the multiplication and summing
• Clear the stored 1024 inputs
• Set all the error bits to zero

• Go back to Step 1 of the detailed description.

• See here for the overall testing plan.
• See here for the testing plan for this module.