L1 FIFO

• The input (set of trigger primitives) contains the following information:
  • Peak timestamp
  • Peak amplitude
  • Trigger word
  • Trigger logic bits
• The input is formatted as an Avalon-ST stream, and does not use channels or packets, unlike other Avalon-ST interfaces used in the L1 trigger firmware.
  • The input stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 72 bit wide data signal, broken down as follows, ordered from the most-significant bits to the least-significant bits:
      • peak timestamp: 32 bits
      • peak amplitude: 16 bits
      • trigger word: 16 bits
      • trigger logic bits: 8 bits
    • 1 bit wide valid signal
  • When the input comes from the Random Trigger module or the External Trigger and Veto module, the meaning of the input changes slightly. The timestamp is still the same, but the peak amplitude is set to a code indicating the source of the trigger (or veto), the trigger word is set to all bits 0, and the trigger logic bits are all set to 1.
  • Note that the trigger word is, as described on the PS module design page, composed of an 8-bit "at-peak trigger word" and an 8-bit "during-window trigger word". The "at-peak trigger word" is found in the most-significant 8 bits of the 16-bit trigger word, and the "during-window trigger word" is found in the least-significant 8 bits of the 16-bit trigger word. Further note that this semantic information does not impact the design of the L1 FIFO module.

• Trigger FIFO pop: 0 bits
  (Writing any value to the address of this register causes the trigger FIFO to "pop", or discard the current head and move on to the next entry. Note that the value written to this address is irrelevant and ignored, which is why it is marked as "0 bits". Only the fact that a write request occurred, and no actual written data, is passed to the L1 FIFO module. This makes it a control input but not a configuration input.)
• Veto FIFO pop: 0 bits
  (As with the "trigger FIFO pop" register, writing any value to the address of this register causes the veto FIFO to "pop", or discard the current head and move on to the next entry. Note that the value written to this address is irrelevant and ignored, which is why it is marked as "0 bits". Only the fact that a write request occurred, and no actual written data, is passed to the L1 FIFO module. This makes it a control input but not a configuration input.)
• Current timestamp $R$: 32 bits
  (This is a counter that is incremented by the DCRC every time a phonon ADC sample is stored into memory (a rate of 625 kHz). It is set to zero at the beginning of a series, and so it records the number of phonon samples recorded since the series start. It will roll over to zero about every 2 hours, which is more than long enough to avoid any ambiguity for the MIDAS front-end.)
• 100 MHz clock input
• 1 reset input

Unlike all the other modules in the L1 trigger design, this module does not send any output as an Avalon-ST stream. Instead, the L1 FIFO module sends any output information by responding to register read requests. Register read requests are a feature of the DCRC in general, not specific to the trigger. MIDAS (or any computer program which connects to the DCRC via the DCRC's ethernet port using the telnet protocol) sends a code that signals a read request. This is followed by a hexadecimal number indicating the address of the register to read. Then, the DCRC sends back a 16-bit value, which is the response to the read request. Note that, if MIDAS (or other telnet client) needs to obtain some information which is longer than 16 bits, such as a 72-bit set of trigger primitives, then multiple read requests are required.

The L1 FIFO module responds to read requests that specify any of seventeen different addresses. Those addresses are listed in the DCRC Register map, and are not reproduced here because they may be subject to future changes. Five of the addresses are used to read out the information (the trigger primitives) that are stored in the trigger FIFO. Three addresses are used to read out the information stored in the veto FIFO. The remaining nine addresses are used to obtain the number of entries in the trigger FIFO, the number of entries in the veto FIFO, the amount of live time accumulated in this series (three registers), the amount of dead time accumulated in this series (three registers), and the number of triggers lost due to dead time.

The seventeen register addresses that the L1 FIFO module responds to are as follows:

1. Trigger FIFO word 4: 16 most-significant bits of the 32-bit peak timestamp
2. Trigger FIFO word 3: 16 least-significant bits of the 32-bit peak timestamp
3. Trigger FIFO word 2: peak amplitude
4. Trigger FIFO word 1: trigger word
5. Trigger FIFO word 0: trigger logic bits (these are only 8 bits, so they are returned in the least-significant 8 bits of the 16-bit register, and the most-significant 8 bits are all set to 0)
6. Veto FIFO word 2: 16 most-significant bits of the 32-bit veto timestamp
7. Veto FIFO word 1: 16 least-significant bits of the 32-bit veto timestamp
8. Veto FIFO word 0: Veto type code:
   • Bit 0 indicates whether this is the beginning of a veto period (bit 0 = 0) or the end of a veto period (bit 0 = 1)
   • Bits 15-1 indicate the source of the veto:
     • 0: veto due to full trigger FIFO
     • 1: veto from ETV module
     • 2 and higher: reserved for possible future use
9. Trigger FIFO length: how many entries are currently in the trigger FIFO
10. Veto FIFO length: how many entries are currently in the veto FIFO
11. Live-time scaler word 2: the 16 most-significant bits of the live-time scaler
12. Live-time scaler word 1: the 16 middle bits of the live-time scaler
13. Live-time scaler word 0: the 16 least-significant bits of the live-time scaler
14. Dead-time scaler word 2: the 16 most-significant bits of the dead-time scaler
15. Dead-time scaler word 1: the 16 middle bits of the dead-time scaler
16. Dead-time scaler word 0: the 16 least-significant bits of the dead-time scaler
17. Lost-trigger counter: how many triggers were unable to be recorded because we were in a veto period

Note that the five addresses used to read out the trigger FIFO and the three addresses used to read out the veto FIFO all return information from the current FIFO "head". Repeated reads will return the same information. To "pop" either FIFO and move on to the next FIFO entry, write to the respective register addresses listed above.

The trigger FIFO length and veto FIFO length registers always contain the number of entries currently in the respective FIFOs. The live-time scaler, dead-time scaler, and lost-trigger counter are set to 0 at the beginning of a data-taking series or when a reset occurs.

This module requires some information to be retained from one time step to the next. It will be stored in internal registers. They are mentioned and named here in order to simplify the detailed description of the module's functionality given below. Note that the information in the "live-time scaler", "dead-time scaler", and "lost-trigger counter" internal registers is accessible via register read requests (see the outputs section above).

• Veto state: 2 bits
  The veto state register indicates whether we are currently accepting or vetoing triggers. The value in this register is incremented when a veto period starts and decremented when it ends. When the veto state register is 0, triggers are accepted and stored into the trigger FIFO as normal. When the veto state register is non-zero, then triggers are not written into the trigger FIFO.
• Live-time scaler: 48 bits
  This register counts the total amount of time during which the trigger is live (able to accept triggers, i.e. the "veto state" internal register is 0). The live time is measured in units of 1.6 μs, the same units as the Current Timestamp. This is 48 bits so that it won't overflow in a long series.
• Dead-time scaler: 48 bits
  This register counts the total amount of time during which the trigger is dead (not accepting triggers, i.e. the "veto state" internal register is non-zero). The dead time is measured in units of 1.6 μs, the same units as the Current Timestamp. This is 48 bits so that it won't overflow even if we have a really bad series with more than 2 hours of deadtime.
• Lost-trigger counter: 16 bits
  This register counts the number of triggers that were received (but not recorded) during veto periods, that is, while the "veto state" internal register is non-zero.

The module detects and reports several possible erroneous conditions via a register read. The value read out consists of 16 bits; the most-significant bits are unused.

• Bit 0: Read or write to invalid register address
• Bit 1: Attempted write to read-only register address
• Bit 2: Veto FIFO full
• Bit 3: "Veto state" counter overflow -- missed an end-veto message
• Bit 4: "Veto state" counter underflow -- missed a start-veto message

The L1 FIFO module performs three tasks: it stores information needed by the L2 trigger, it provides that information to the L2 trigger via register read requests, and it tracks trigger dead time. The L2 trigger needs this information both to make the L2 trigger decision and to read out each event.

The L2 trigger needs the set of trigger primitives associated with each L1 trigger: the peak timestamp, the peak amplitude, the trigger word, and the trigger logic bits (all as described on the Peak Search and Trigger Logic pages). These are stored into a "trigger FIFO" located in the FPGA internal memory, and they can be read by the L2 trigger via register read requests. More details are below.

There are some periods of time during which, for a variety of reasons, the L1 trigger is unable to record triggers. There are two sources of trigger dead time: external vetos generated by the ETV module, and overflow of the trigger FIFO (when the trigger FIFO is full, no more L1 triggers can be recorded). At the start and end of every such "veto period", a timestamp and type code will be recorded into a "veto FIFO", also located in the FPGA internal memory. The timestamp will indicate the time at which the veto period started or ended. The type code will indicate whether the timestamp represents the start or end of a veto period as well as some indication about the cause of the veto period. The timestamp and type code can also be read by the L2 trigger via register read requests. More details are below.

Each input word either represents an L1 trigger or else it represents a veto start or stop. The L1 FIFO module must identify which is which and write the information to the appropriate FIFO. This determination is based on the trigger word and the peak amplitude. For normal, data-based triggers, the trigger word will have at least one bit set. For veto start/stop inputs, as well as for special purpose triggers (random triggers and external triggers), all the bits of the trigger word will be zeros. If the trigger word is all zeros, then the final determination is made based on the peak amplitude, which will be set to a code indicating the type of input: 0 for random triggers, 1 for veto starts, 2 for veto stops, and 3 or more for external triggers.

When a normal trigger, a random trigger, or an external trigger is received, it will be written to the trigger FIFO if we are not in a veto period and if the trigger logic bits are not all zeros. When a veto start or veto stop is received, or when the trigger FIFO becomes full or is emptied again, an entry will be written to the veto FIFO and the "veto state" internal register will be adjusted. When a veto start is received or when the trigger FIFO becomes full, the "veto state" internal register will be incremented. When a veto stop is received or when the trigger FIFO is read out (and therefore no longer full), the "veto state" internal register will be decremented.

In addition to recording the beginning and end of each veto period, the L1 FIFO module also tracks the amount of live time and dead time during the series, as well as the number of triggers that were received but not written to the trigger FIFO during veto periods. Each time the least-significant bit of the "current timestamp" changes, the "veto state" internal register is checked. If the "veto state" internal register is zero, then the "live-time scaler" internal register is incremented. If the "veto state" internal register is non-zero, then the "dead-time scaler" internal register is incremented instead. When a trigger is received during a veto period, the "lost-trigger counter" internal register is incremented. These three internal registers can each be read out via register read requests.

FIFO Technical Details

Both FIFOs, the trigger FIFO and the veto FIFO, are implemented as Altera SCFIFO IP Cores (also known as "lpm_fifo"). This IP Core has the following input signals (that we will use):

• clock (1 bit wide): this clock is used to synchronize all input and output operations
• data (configurable bit width): this signal holds the data which will be written in to the FIFO when the "wrreq" signal is asserted
• wrreq (1 bit wide): when this signal is asserted on a rising clock edge, the data on the "data" signal is written in to the FIFO
• rdreq (1 bit wide): when this signal is asserted on a rising clock edge, the FIFO will be popped, discarding the entry at the head of the FIFO

• q (configurable bit width): this signal holds the data that is currently at the head of the FIFO
• full (1 bit wide): this signal will be asserted when the FIFO is full and no more data can be written
• usedw (configurable bit width): this signal indicates the number of entries that are currently stored in the FIFO

• lpm_width: this parameter sets the bit widths of the "data" and "q" signals
• lpm_widthu: this parameter sets the bit width of the "usedw" signal
• lpm_numwords: this parameter sets the number of entries that can be stored in the FIFO
• lpm_showahead: this parameter controls whether the FIFO head is available on the "q" signal at all times, or only following assertion of the "rdreq" signal.

Trigger FIFO Technical Details

For the trigger FIFO, which stores the trigger primitives, we will use an 80-bit wide FIFO which is 256 entries deep. That is, "lpm_width" will be set to 80, "lpm_numwords" will be set to 256, and "lpm_widthu" will be set to 16. Additionally, "lpm_showahead" will be set to "ON", meaning that the FIFO head will be available on the "q" signal at all times, and thus the "rdreq" signal is only used to pop the FIFO. The trigger FIFO is 80 bits wide because that is the smallest multiple of 16 bits that is large enough to hold a set of trigger primitives (which is 72 bits: 32-bit peak timestamp, 16-bit peak amplitude, 16-bit trigger word, and 8-bit trigger logic bits). Using a multiple of 16 makes it easier set up the FIFO readout registers "Trigger FIFO Words 0-4".

When a normal trigger, random trigger, or external trigger is received, the trigger logic bits are checked. As long as at least one of the trigger logic bits is set, then the "veto state" internal register is also checked. If the "veto state" internal register is zero, then the trigger will be written to the trigger FIFO. This is accomplished by setting the "data" signal to the trigger primitives (note that the 8 trigger logic bits are padded with 8 zero bits to fill the trigger primitives out to 80 bits -- this is done to make the register readout slightly easier), and then asserting the "wrreq" signal for one clock cycle.

After writing to the trigger FIFO, the trigger FIFO "full" signal will be checked. If the trigger FIFO has become full, then an entry will be written to the veto FIFO and the "veto state" internal register will be incremented.

Some of the output registers ("trigger FIFO words 0-4" and "trigger FIFO length") must use information from the trigger FIFO's signals.

• Reading from the "trigger FIFO length" output register returns the current value of the "usedw" signal.
• Reading from the "16 most-significant bits of the 32-bit peak timestamp" output register returns bits 79-64 of the "q" signal (the most-significant 16 bits).
• Reading from the "16 least-significant bits of the 32-bit peak timestamp" output register returns bits 63-48 of the "q" signal (the second-most-significant 16 bits).
• Reading from the "peak amplitude" output register returns bits 47-32 of the "q" signal (the third-most-significant 16 bits).
• Reading from the "trigger word" output register returns bits 31-16 of the "q" signal (the fourth-most-significant 16 bits).
• Reading from the "trigger logic bits" output register returns bits 15-0 of the "q" signal (the least-significant 16 bits).

The control input register "trigger FIFO pop" uses the trigger FIFO's signals as well. When a write request for the "trigger FIFO pop" register address is received, the "rdreq" signal will be asserted for one clock cycle. This pops the trigger FIFO. Note that, before the trigger FIFO is popped, the trigger FIFO "full" signal will be checked. If the trigger FIFO was full before being popped, then it will no longer be full after being popped, and so an entry will be made in the veto FIFO and the "veto state" internal register will be decremented.

Veto FIFO Technical Details

For the veto FIFO, which stores the veto period information, we will use a 48-bit wide FIFO which is 256 entries deep. That is, "lpm_width" will be set to 48, "lpm_numwords" will be set to 256, and "lpm_widthu" will be set to 16. Additionally, "lpm_showahead" will be set to "ON", meaning that the FIFO head will be available on the "q" signal at all times, and thus the "rdreq" signal is only used to pop the FIFO. The 48-bit width of the veto FIFO is chosen because it is the smallest multiple of 16 bits that is large enough to hold all the information it needs to store (the 32-bit timestamp plus a few bits for the veto type code). Using a multiple of 16 makes it easier set up the FIFO readout registers "Veto FIFO Words 0-2".

When a veto start or veto stop is received from the ETV module, or when the trigger FIFO becomes full or is emptied again, the received timestamp (for external vetos) or the current timestamp (for full-trigger-FIFO vetos), along with the veto type code described above is written to the veto FIFO. This is accomplished by setting the "data" signal to the timestamp and veto type code and then asserting the "wrreq" signal for one clock cycle.

Vetos should be rare enough that the veto FIFO will never become full. During testing and early operations at SNOLAB, we will check to see that the veto FIFO does not ever become close to full. If it is not deep enough, then we will increase the veto FIFO depth enough that it will never become full during normal operations. We note that, while there may occasionally be some pathological conditions which would cause the veto FIFO to fill much faster than normal, any data series during which this occurs would almost certainly be marked bad for physics analysis. Furthermore, such a pathological condition would be obvious because the veto FIFO would contain many more entries than normal. Thus, no special handling of a full veto FIFO is needed.

Some of the output registers ("veto FIFO words 0-2" and "veto FIFO length") must use information from the veto FIFO's signals.

• Reading from the "veto FIFO length" output register returns the current value of the "usedw" signal.
• Reading from the "16 most-significant bits of the 32-bit veto timestamp" output register returns bits 47-32 of the "q" signal (the most-significant 16 bits).
• Reading from the "16 least-significant bits of the 32-bit veto timestamp" output register returns bits 31-16 of the "q" signal (the second-most-significant 16 bits).
• Reading from the "veto type code" output register returns bits 15-0 of the "q" signal (the least-significant 16 bits).

The control input register "veto FIFO pop" uses the veto FIFO's signals as well. When a write request for the "veto FIFO pop" register address is received, the "rdreq" signal will be asserted for one clock cycle. This pops the veto FIFO.

The L1 FIFO module performs four tasks in parallel. Each of the subheadings below describes a sequences of steps which must be performed when certain events occur, such as an input being received or a register read request being received. The full list of tasks is:

1. Steps to perform when an input is received
2. Steps to perform when the least-significant bit of the "current timestamp" input changes
3. Steps to respond to a register read request
4. Steps to handle a register write request

1. Subroutine to write to the trigger FIFO
2. Subroutine to record a veto

Steps to perform when an input is received:

1. When an input is received, we either perform the steps listed under "Subroutine to write to the trigger FIFO" or perform the steps listed under "Subroutine to record a veto". To determine which one to do, examine the trigger word and the peak amplitude. The next steps to take depend on the values of the trigger word and the peak amplitude.
   • If the trigger word is not all zeros, then this input is a normal data-driven trigger. Examine the trigger logic bits:
     • If all of the 8 trigger logic bits are FALSE, then ignore this trigger and do not perform any of the subsequent steps.
     • If any of the 8 trigger logic bits are TRUE, then perform the steps listed under "Subroutine to write to the trigger FIFO".
   • If the trigger word is all zeros, and the peak amplitude is 0, then this input is a random trigger. Perform the steps listed under "Subroutine to write to the trigger FIFO".
   • If the trigger word is all zeros, and the peak amplitude is 1 or 2, then this input is an external veto start or stop. Perform the steps listed under "Subroutine to record a veto".
   • If the trigger word is all zeros, and the peak amplitude is 3 or more, then this input is an external trigger. Perform the steps listed under "Subroutine to write to the trigger FIFO".

Steps to perform when the least-significant bit of the "current timestamp" input changes:

1. Examine the "veto state" internal register:
   • If it is zero, then increment the "live-time scaler" internal register.
   • If it is non-zero, then increment the "dead-time scaler" internal register.

Steps to respond to a register read request:

As previously mentioned, this module responds to register read requests on 17 different register addresses: 5 register addresses for reading out the trigger FIFO, 3 register addresses for reading out the veto FIFO, 1 register address for the number of entries currently in the trigger FIFO, 1 register address for the number of entries currently in the veto FIFO, 3 register addresses for the live-time scaler, 3 register addresses for the dead-time scaler, and 1 register address for the number of triggers lost due to a full FIFO. Here we describe how the module responds to a read request for each of these addresses.

1. Examine the address of the register read request and send back the bits described in the following table.

Steps to handle a register write request:

This module takes action based upon writes to two register addresses, one is used to pop the trigger FIFO and one is used to pop the veto FIFO. Note that the value that is "written" to these registers is completely ignored; the action of sending a write request causes the L1 FIFO module to perform some actions. Further note that the telnet client does not expect any response to a write request.

1. Examine the address of the register write request:
   • If it is for the "trigger FIFO pop" register, then pop the trigger FIFO:
     1. Examine the trigger FIFO "full" signal:
        • If it is TRUE, then the trigger FIFO was full and will no longer be full after it is popped. That is, the veto period caused by the full trigger FIFO is ending. Perform the steps listed under "Subroutine to record a veto". In parallel, continue on to the next step.
        • If it is FALSE, then simply continue on to the next step.
     2. Set the trigger FIFO "rdreq" signal to TRUE
     3. On the next clock cycle, set the trigger FIFO "rdreq" signal to FALSE
   • If it is for the "veto FIFO pop" register, then pop the veto FIFO:
     1. Set the veto FIFO "rdreq" signal to TRUE
     2. On the next clock cycle, set the veto FIFO "rdreq" signal to FALSE

Subroutine to write to the trigger FIFO

1. Examine the "veto state" internal register:
   • If the "veto state" internal register is zero, then we are not in a veto period. Continue to step 2.
   • If the "veto state" internal register is non-zero, then we are in a veto period. Increment the "lost-trigger counter" internal register and do not perform any of the subsequent steps.
2. Set the "data" signal of the trigger FIFO to the input trigger primitives. Note that bits 15-8 of the "data" signal are set to all zeros to pad the trigger logic bits. Concurrently, set the "wrreq" signal of the trigger FIFO to TRUE.
3. On the next clock cycle, set the "wrreq" signal of the trigger FIFO back to FALSE.
4. On the next clock cycle, examine the "full" signal of the trigger FIFO:
   • If the "full" signal is FALSE, then the trigger FIFO is not yet full, so take no further action.
   • If the "full" signal is TRUE, then the trigger FIFO is full, so perform the steps listed under "Subroutine to record a veto".

Subroutine to record a veto

1. Increment (in the case of the beginning of a veto period) or decrement (in the case of the end of a veto period) the "veto state" internal register.
2. Set the "data" signal of the veto FIFO to represent this veto period beginning or end:
   • Set bits 47-16 to either the input timestamp (in the case of an external veto) or to the current timestamp (in the case of a full-trigger-FIFO veto)
   • Set bits 15-1 to indicate the source of the veto: 0 in the case of a full-trigger-FIFO veto or 1 in the case of an external veto
   • Set bit 0 to either 0 (in the case of a veto period beginning) or 1 (in the case of a veto period end)
   Concurrently, set the "wrreq" signal of the veto FIFO to TRUE.
3. On the next clock cycle, set the "wrreq" signal of the veto FIFO to FALSE.

Reset Signal:

• Set the "veto state" internal register to 0.
• Set the "live-time scaler" internal register to 0.
• Set the "dead-time scaler" internal register to 0.
• Set the "lost-trigger counter" internal register to 0.
• Empty both the trigger FIFO and the veto FIFO
• Set all the error bits to zero

• Resume normal operations.

• The initial version of the L1 FIFO module has already been written by Sten Hansen for the Rev D DCRC. It will need to be altered somewhat, because it is designed to handle the simple triggering that is currently available in the Rev D firmware, but the basic functionality of writing to memory and reading the registers is already written. For this reason, the details of how responding to register read requests is accomplished have been left out of this design document.
• ¹ The TrL, RT, and ETV modules each produce one Avalon-ST stream as their output. In order to keep the L1 FIFO module simple, the L1 FIFO module only has one Avalon-ST input. Therefore, we insert an Altera Avalon-ST Multiplexer module between the L1 FIFO module and the TrL, RT, and ETV modules. The multiplexer takes in 3 input streams and produces a single output stream, which is then the input to the L1 FIFO module.