Random Trigger (RT)

Note that there is no data input to this module. All the inputs, like the current timestamp, are from the Configuration and Control Inputs.

• 1 Random Trigger Threshold $T$: 32 bits
• Current timestamp $R$: 32 bits
  (This is a counter that is incremented by the DCRC every time a phonon ADC sample is stored into memory (a rate of 625 kHz). It is set to zero at the beginning of a series, and so it records the number of phonon samples recorded since the series start. It will roll over to zero about every 2 hours, which is more than long enough to avoid any ambiguity for the MIDAS front-end.)
• 100 MHz clock input
• 1 reset input

Note that the threshold is set during initialization¹ at the start of running and is expected to remain the same after that, but it can be changed at any time if needed.

There is 1 streaming output, which goes directly to the L1 FIFO module:

• The output (fake Trigger Primitive) contains the following information:
  • Timestamp of the random triggers
  • Peak amplitude, which for random triggers is all zeros
  • Trigger word, which for random triggers is all zeros
  • Trigger logic bits, which for random triggers is all ones
• The output is formatted as an Avalon-ST stream, and does not use channels or packets, unlike other Avalon-ST interfaces used in the L1 trigger firmware.
• The output stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
  • 72 bit wide data signal, broken down as follows, ordered from the most-significant bits to the least-significant bits:
    • timestamp: 32 bits
    • peak amplitude: 16 bits (all set to 0)
    • trigger word: 16 bits (all set to 0)
    • trigger logic bits: 8 bits (all set to 1)
  • 1 bit wide valid signal

The module detects and reports several possible erroneous conditions via a register read. The value read out consists of 16 bits; the most-significant bits are unused.

• Bit 0: Read or write to invalid register address
• Bit 1: Invalid value written to register

The primary goal of this module is to provide an unbiased selection of noise from the detectors. This module generates a random number, $R$, every time a phonon ADC sample is recorded into memory (a rate of 625 kHz), and compares it to the threshold, called $T$, to produce a set of fake Trigger Primitives for use in the L1 FIFO. Since the random number and threshold are 32 bits wide, the minimum rate of random triggers produced by this module is \(\frac{625~\mathrm{kHz}}{2^{32}}\), which is one random trigger roughly every 2 hours or 0.00014 Hz. Later, the data acquisition system reads out the data corresponding to these random timestamps. Because the random selection of time stamps proceeds completely independently from everything else, not even sharing computing resources, this is a fully unbiased timestamp selection.

Step-by-step:

Do the following each time the least significant bit (LSB) of the current timestamp changes (from 0 to 1 or from 1 to 0):

1. Generate a random number $R$.
2. Compare the random number $R$ to the random trigger threshold $T$:
   • If $R \ge T$, do nothing.
   • If $R \lt T$, set the 72 data bits in the output as follows:
     • Set the most-significant 32 data bits to the current timestamp
     • Set the next-most-significant 32 data bits to all zeros
     • Set the least-significant 8 data bits to 11111111
     Concurrently, set the valid bit. On the next clock cycle, unset the valid bit.

Reset Signal:

• Set the random trigger threshold to zero
• Set all the error bits to zero

• Go back to Step 1 of the detailed description.

• See here for the overall testing plan.
• See here for the testing plan for this module.