Trigger Logic (TrL)

• The input (set of trigger primitives) contains the following information:
  • Peak timestamp
  • Peak amplitude
  • Trigger word
• The input is formatted as a 4-channel Avalon-ST stream, and does not use packets unlike other Avalon-ST interfaces used in the L1 trigger firmware.
  • The input stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 64 bit wide data signal, broken down as follows, ordered from the most-significant bits to the least-significant bits:
      • peak timestamp: 32 bits
      • peak amplitude: 16 bits
      • trigger word: 16 bits
    • 2 bit wide channel-number signal (to indicate which of the 4 PS submodules produced each input)
    • 1 bit wide valid signal
  • Note that each PS submodule sends an input independently of the other 3 PS submodules, and the inputs come intermittently, not synchronously with any data flow earlier in the L1 trigger firmware.
  • Note that the trigger word is, as described on the PS module design page, composed of an 8-bit "at-peak trigger word" and an 8-bit "during-window trigger word". The "at-peak trigger word" is found in the most-significant 8 bits of the 16-bit trigger word, and the "during-window trigger word" is found in the least-significant 8 bits of the 16-bit trigger word. Further note that this semantic information does not impact the design of the TrL module.

• Require Masks \(R_i\): 16 bits/Mask, 1 Mask/output trigger bit, 8 output trigger bits
• Veto Masks \(V_i\): 16 bits/Mask, 1 Mask/output trigger bit, 8 output trigger bits
• Trigger Logic Selectors \(S_i\): 2 bits/Selector, 1 Selector/output trigger bit, 8 output trigger bits
• Prescale Probabilities \(P_i\): 16 bits/Probability, 1 Probability/output trigger bit, 8 output trigger bits
• Enable Bits \(E_i\): 1 bit each, 1 Enable Bit/output trigger bit, 8 output trigger bits
• 100 MHz clock input
• 1 reset input

Note that the Masks, Selectors, Probabilities, and Enable Bits are set during initialization¹ at the start of running and are expected to remain the same after that, but they can be changed at any time if needed.

• The output (set of trigger primitives) contains the following information:
  • Peak timestamp, passed through this module unaltered
  • Peak amplitude, passed through this module unaltered
  • Trigger word, passed through this module unaltered
  • Trigger logic bits
• The output is formatted as an Avalon-ST stream, and does not use channels or packets, unlike other Avalon-ST interfaces used in the L1 trigger firmware.
  • The output stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 72 bit wide data signal, broken down as follows, ordered from the most-significant bits to the least-significant bits:
      • peak timestamp: 32 bits
      • peak amplitude: 16 bits
      • trigger word: 16 bits
      • trigger logic bits: 8 bits
    • 1 bit wide valid signal
  • Note that the output is in lockstep with the input in the event of a set of trigger primitives arriving from the PS module, with a latency that will be measured later.
  • The most significant 64 bits of the output are merely passed through from the input from PS module. The least significant 8 bits are computed by the TrL module.
  • Although the input is a 4-channel stream, the output does not include channel numbers (making it a de facto 1-channel stream) -- the channel number from the input is used by this module but not passed on to the L1 FIFO.

The module detects and reports several possible erroneous conditions via a register read. The value read out consists of 16 bits; the most-significant bits are unused.

• Bit 0: Read or write to invalid register address
• Bit 1: Invalid value written to register
• Bit 2: Require and Veto masks are inconsistent
• Bit 3: All submodules are disabled
• Bit 4: Selector set to illegal value
• Bit 5: Illegal channel number in input
• Bit 6: At-peak and During-window trigger words in input are inconsistent

This module makes the L1 trigger decisions based on the 16 bits of the input trigger word. The L1 FIFO will, based on these L1 trigger decisions, record or discard each set of trigger primitives produced by the PS submodules. The trigger primitives produced by the PS modules are passed through this module along with 8 additional bits (the "trigger logic bits"), which are computed by this module. These 8 trigger logic bits represent the L1 trigger decision. That is, the L1 FIFO will record the trigger primitives (including the 8 trigger logic bits) if any of the 8 trigger logic bits is TRUE.

This module makes the trigger decision by using 8 pairs of 16-bit bitmasks: a "Require Mask" \(R_i\) (to define which bits of the trigger word are required to be 1) and a "Veto Mask" \(V_i\) (to define which bits of the trigger word are required to be 0). This module checks each incoming trigger word, making sure that all bits set in the "Require Mask" \(R_i\) are 1 in the trigger word, and that all bits set in the "Veto Mask" \(V_i\) are 0 in the trigger word. This check is repeated 8 times, once for each mask pair.

In addition to this trigger word check, for each mask pair there is a "Trigger Logic Selector" \(S_i\) which selects which of the 4 PS submodules the mask pair is associated with, an "Enable Bit" \(E_i\) that allows the corresponding output bit to be switched off, and a prescale bit which is derived from the comparison of a random number \(x_i\) (which is generated internally in this module) against a threshold \(P_i\) allowing triggers to be rejected probabilistically. Each "Trigger Logic Selector" \(S_i\) is compared with the channel number $C$ associated with the input, yielding a TRUE bit if they are the same and FALSE otherwise. The logical AND of the trigger word check, the Selector check, the Enable Bit, and the prescale bit determines the corresponding bit in the output. The 8 bits are sent to the L1 FIFO, where they are used to determine whether the set of trigger primitives should be stored or discarded.

An example of how the TrL module would handle a (simplified) sample input is given in Table 1, where the input trigger word (labeled $T$ in the table) is 1010 and the input channel number is 0, indicating that this input came from PS submodule 0 (which in turn gets its input from FIR submodule 0 and LC submodule 0). Note that we have used a 4 bit example for simplicity, rather than the full 16 bits in the actual trigger firmware. There are 8 rows in the table, one for each of the 8 trigger bits. The columns show how each of the 8 output bits is computed. For our example input, the final result is a 1 for the first bit (Bit 0), and the rest are all 0, but they are 0 for different reasons (discussed in the next paragraph). For Bit 0, the computations (described more mathematically in the Step-by-Step description below) go as follows:

• The Require Mask, \(R_0\), is 1010 -- that is, bit 0 and bit 2 are set. Since bit 0 and bit 2 are also set in the trigger word (also 1010), this trigger can pass. Said differently, \(((T \mathrel{\&} R_0) \mathrel{==} R_0) = 1\)
• Similarly, the Veto Mask, \(V_0\), is 0100 -- that is, bit 1 is set. Since bit 1 is not set in the trigger word (1010), the trigger is not vetoed. Said differently, \(((\sim\!T \mathrel{\&} V_0) \mathrel{==} V_0) = 1\).
• There is no prescale (the Prescale Probability \(P_0\) is 0), so it has no effect. The random number generated (in this example \(x_0 = 49732\)) is greater than or equal to 0, so the output bit is a 1.
• This is Channel 0, and since we are considering this channel as specified by the Selector (\(S_0 = 0\)), the Selector check bit is a 1.
• This output bit is enabled (\(E_0\mathrel{=}1\)), so we get a 1.

For the other bits, we simply specify why they aren't set to 1 (they fail to trigger). Bit 1 is 0 because one of the bits in the Require Mask (the last bit) is not present in the trigger word. Bit 2 is 0 because of the prescale. Bit 3 is 0 because one of the bits in the Veto Mask (the third bit) is present in the trigger word. Bit 4 is 0 because the Enable Bit is 0 (this trigger bit is disabled). Bit 5 is 0 because the channel number does not match the Selector (it is designed for a different channel). Bit 6 is 0 for multiple reasons: the required bits are not set in the trigger word, the vetoed bits are set in the trigger word, and the channel number does not match the Selector. Bit 7 is also 0 for multiple reasons: the channel number does not match the Selector, and the Enable Bit is 0.

Table 1

Step-by-step:

1. Receive input from any of the 4 PS submodules. Each datum will have a "channel number" attached to it, indicating which PS submodule it came from.
2. The 8 output trigger logic bits are each computed as the logical AND of five bits, the details of which are specified by the Configuration and Control Inputs. The computation of the \(i\)th output trigger logic bit uses
   • Data inputs:
     • the input channel number \(C\),
     • the input trigger word \(T\).
   • Configuration inputs:
     • the \(i\)th Trigger Logic Selector \(S_i\),
     • the \(i\)th Enable Bit \(E_i\),
     • the \(i\)th Prescale Probability \(P_i\),
     • the \(i\)th Require Mask \(R_i\),
     • the \(i\)th Veto Mask \(V_i\).
   • Module determined:
     • a 32-bit random number \(x_i\) obtained from the pseudo-random number generator².
   All of the checks described below (8 copies each of 5 checks) are performed in parallel and then combined in 8 copies of a 5-bit AND operation (the 8 AND operations are also done in parallel). The \(i\)th copy of the 5 bits for the AND are as follows:
   • Trigger word comparison with the \(i\)th Require Mask: \[(T \mathrel{\&} R_i) \mathrel{==} R_i\] where $T$ is the trigger word and $R_i$ is the \(i\)th Require Mask. The logical operations are notated as in the C programming language, so that $\mathrel{\&}$ is a bitwise logical AND and $\mathrel{==}$ is a test for equality of all bits. The \(i\)th Require Mask is one of the Configuration and Control Inputs.
   • Trigger word comparison with the \(i\)th Veto Mask: \[(\sim\!T \mathrel{\&} V_i) \mathrel{==} V_i\] where $T$ is the trigger word and $V_i$ is the \(i\)th Veto Mask. The logical operations are notated as in the C programming language, so that $\mathrel{\&}$ is a bitwise logical AND, $\sim$ is a bitwise logical negation, and $\mathrel{==}$ is a test for equality of all bits. The \(i\)th Veto Mask is one of the Configuration and Control Inputs.
   • The \(i\)th Pre-scale bit: $x_i \geq P_i$, where $x_i$ is a pseudo-random number, and $P_i$ is the \(i\)th Prescale Probability (one of the Configuration and Control Inputs).
   • The \(i\)th Selector bit: \(C \mathrel{==} S_i\), where $C$ is the channel number of the input (indicating which PS module the input came from), and $S_i$ is the \(i\)th Trigger Logic Selector (one of the Configuration and Control Inputs).
   • The \(i\)th Enable Bit: \(E_i \mathrel{==} 1\) (one of the Configuration and Control Inputs)
   That is, the \(i\)th output bit is \[(C \mathrel{==} S_i) \land E_i \land (x_i \geq P_i) \land ((T \mathrel{\&} R_i) \mathrel{==} R_i) \land ((\sim T \mathrel{\&} V_i) \mathrel{==} V_i),\] where $\mathrel{==}$ is a test for equality of all bits, $\land$ is a Boolean AND, $\mathrel{\&}$ is a bitwise AND, and $\sim$ is a bitwise negation.
3. Concatenate the 8 bits calculated above, append them to the 64 bits of input, and set the resulting 72 bits as the 72 data bits of the output. Concurrently, set the valid bit.
4. On the next clock cycle, unset the valid bit.
5. Return to step 1

Reset Signal:

• Set all the masks, prescales, selectors, and enable bits to all zeros
• Reset the subsystem that monitors the input packets and checks them for errors
• Set all the error bits to zero

• Go back to Step 1 of the detailed description.

• ² The pseudo-random number generator is a standard IP component provided by Altera. It sends pseudo-random numbers via an Avalon-ST streaming interface. To obtain a single random number, this block must assert the "ready" signal on the Avalon-ST interface for one clock cycle.

• See here for the overall testing plan.
• See here for the testing plan for this module.