Analog-to-Digital Converter(ADC)

There are 5 separate outputs, one from each ADC chip on the DCRC, which go to the DF module.

• The 5 outputs contain the following information:
  • phonon channels 1-4
  • phonon channels 5-8
  • phonon channels 9-12
  • charge channels 1-2
  • charge channels 3-4
• The output is not formatted as an Avalon-ST stream unlike other streaming interfaces used in the L1 trigger firmware. The format is described in more detail later on this page.
  • Each output includes the following signals:
    • Data signal:
      • 56 wires for each phonon output (4 phonon channels with 14 bits each in parallel)
      • 32 wires for each charge output (2 charge channels with 16 bits each in parallel)
    • 1 bit wide ready signal
  • Note that the output samples go to the Downsample Filter (DF) module in groups: 3 groups of 4 phonon channels each at a rate of 625 kHz, and 2 groups of 2 charge channels each at a rate of 2.5 MHz. The output samples are presented on parallel signals, and are accompanied by a "ready" signal. When the ready signal for each output is asserted, the data for that output is available on the next rising edge of the 100 MHz clock.

Background information

We will begin with some fine details that are not strictly necessary for understanding the interface to the L1 trigger code, but are helpful for gaining an understanding of what is actually going on in the DCRC. In the next section we describe the interface to the L1 trigger code.

There are 5 physical ADC chips on the DCRC. Three of them are phonon ADC chips, and two are charge ADC chips. Each of the three phonon ADC chips contains 4 parallel ADCs, and each of the two charge ADC chips contains 2 parallel ADCs. The phonon and charge ADC chips are different models. Both are from Linear Technology. The phonon ADC chips are LTC2171-14 chips. The charge ADC chips are LTC2323-16 chips.

The DCRC's FPGA (an Altera Cyclone IV) sends signals to each of the ADC chips to tell them when to convert their analog input to a digital value. These signals are regularly spaced (10 MHz for phonon ADCs and 5 MHz for charge ADCs), and the duration of the signal is determined by the specifications of the ADC chips. These signals are synchronized, so all three phonon ADC chips digitize simultaneously, and similarly both charge ADC chips also digitize simultaneously. However, the phonon ADC chips do not digitize at the same time as the charge ADC chips because the digitization rates are different.

The ADC chips then send the digitized data back to the FPGA as a serial stream of bits. The ADC chips generate (phonon chips) or receive from the FPGA (charge chips) an additional clock signal which governs this transfer of digital data. This difference between generating or receiving the clock signal that governs digital data transfer is a difference in the design of the phonon and charge ADC chips. The FPGA deserializes the received bits, and then it has a set of samples from one ADC chip.

Although the ADC chips digitize their inputs simultaneously, the response time of the digital electronics that send the digitized results back to the FPGA may differ slightly from chip to chip, so the FPGA may eventually receive the samples from different chips at slightly different times (although close enough in time that they can unambiguously be aligned later, for example in the Synchronizer module).

The 10 MHz and 5 MHz sample rates are higher than is actually needed for recording phonon and charge signals. So, the DCRC firmware sums every 16 phonon ADC samples and every 2 charge samples. It oversamples in this way to reduce sensitivity to noise somewhat (wikipedia). Then this downsampled stream of samples is recorded to a circular readout buffer on the DCRC so that the data acquisition system can later read it out as an event.

The circular readout buffer is stored in random-access memory (RAM), and writing to RAM goes through a RAM controller. The accumulators that perform the summing operate on a different clock than the RAM controller. As a result, some mechanism for clock-crossing is needed. When an accumulator has a sum that is ready to be written to RAM, it stores that sum in a register and sets a bit indicating that the data is available in the register. This occurs on, or shortly after, a rising edge of the accumulator's clock. Then, the RAM controller looks at this "ready signal" bit on its own clock's rising edge. When it sees the ready signal bit is set, it takes the data from the register and writes it to RAM. Then, on the next rising edge of its own clock, it unsets the ready signal bit. This way, it is guaranteed that the data will be available at least long enough for the RAM controller to use it.

L1 trigger interface

Now we have enough background information to talk about the trigger. The trigger firmware runs, alongside the other functions of the DCRC, some of which are described above, on the DCRC's FPGA, and so has direct access to the accumulator output signals.

The trigger begins in the DF module by examining the "ready signal" bits on every cycle of the main system clock (which is also the clock used by the accumulators). When the "ready signal" bit is set, the trigger code takes and uses the ADC data.

That is, at the time that the "ready signal" bit for one phonon ADC chip is set, there are 56 wires (4 channels times 14 bits per channel) in the FPGA that are carrying a pattern of bits that represents the sum of the 16 most recent phonon ADC samples. A phonon DF submodule immediately stores those 56 bits into an internal register. Since the values are then stored in an internal register, they will not vanish, so the phonon DF submodule processes them at its leisure. This processing that the phonon DF submodule performs is, of course, described in detail on the DF module page.

The charge channels are handled similarly, except that each charge ADC chip handles 2 charge channels, each of which has 16 bits per channel for a total of 32 wires.