Design and Implementation of the CDMS Level 1 trigger

The diagram below is our current trigger firmware plan as described in the SuperCDMS SNOLAB Conceptual Design Report (Section 9.3). If you click each block here, a page with more details about how we plan to implement it will show up.

• This design, and the details of the processing and data passing, is based on its implementation in the FPGA on the DCRC (Altera Cyclone IV). There is a clock and reset input (we didn't put on the diagram) to each block, and each clock input is at 100MHz clock rate.
• Quick functionality description: the phonon inputs come in from the ADCs at a rate of 625 kHz and the charge inputs come in at a rate of 2.5MHz. After downsampling (implemented in module Down Sample Filter), they come out at a rate of 39.0625 kHz, are synchronised and are pushed through the trigger (implemented in modules Synchronizer, Linear Combination (LC), FIR, Threshold Logic (ThL), and Peak Search (PS)) in lockstep to compute the trigger primitives. The output of PS is asynchronous as it only outputs if it finds a trigger primitive. The Trigger Logic module computes the final L1 trigger decision, and outputs the result to the L1 FIFO. The L1 FIFO will write the trigger primitives into the FIFO or discard them, based on the L1 trigger decision.
• Each dashed box indicates a module. The small boxes (submodules) inside the same large dashed box have the same functions, and are implemented with identical code. Since the inputs to each sub-module may vary the outputs may vary. In many cases, the outputs of the submodules are combined to create a single output from the module.
• In addition to the design we have created a full testing suite which can be found here. Note that this includes testing each module in isolation, both in simulation and hardware on our tester boards, and then we will test the entire trigger (all modules together) in simulation and in hardware on our tester boards, and then we will also test the entire trigger (all modules) on the DCRC (Note we will not do the tests for individual module on the DCRC).
• This trigger firmware design should work with both iZIP and HV detectors. The only change is that the unused ADC inputs on HV DCRCs will need to be hooked up to dummy data.
• This design will use only a small fraction of the FPGA's resources. The FIR and LC modules will use a handful of the FPGA's 150 multiplier blocks, and the L1 FIFO module will use 32 kilobits of the thousands of kilobits of on-chip memory.
• Throughout the design, we will use the "signed" and "unsigned" numeric types from the IEEE "numeric_std" library. This will give us two's-complement integers with a consistent endianness.
• Trigger Frimware Page/Coding Progress