Finite Impulse Response (FIR)

• The input contains the following information:
  • Linear combinations 1-4
• The input is formatted as a 4-channel packetized Avalon-ST stream.
  • The input stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 18 bit wide data signal (which is used to carry the 4 inputs in serial)
    • 2 bit wide channel-number signal (to specify which of the 4 channels each datum belongs to)
    • 1 bit wide valid signal
    • 1 bit wide start-of-packet signal
    • 1 bit wide end-of-packet signal
    • 2 bit wide error signal (unused, so always set to 00)
  • Packets will be received at a rate of 39.0625 kHz.
  • Note that each of the 4 linear combinations is carried on its own Avalon-ST channel. That is, when receiving a sample from LC 1, the Avalon-ST channel number bits will be set to 00. When receiving a sample from LC 2, the channel number bits will be set to 01, etc. That is, samples from LC 1-4 are received on Avalon-ST channels 0-3, respectively.
  • Each packet will consist of exactly 4 data, one from each of the 4 LC submodules. Each FIR submodule will use exactly one datum, the one from the corresponding LC submodule.

• Finite Impulse Response Coefficients $b_{i}$: 16 bits/coefficient, 1024 coefficients/submodule, 4 submodules
• 100 MHz clock input
• 1 reset input

Note that the Finite Impulse Response Coefficients are set during initialization¹ at the start of running and are expected to remain the same after that, but they can be changed at any time if needed.

• The output contains the following information:
  • Trigger waveforms 1-4
• The output is formatted as a 4-channel packetized Avalon-ST stream.
  • The output stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
    • 16 bit wide data signal (which is used to carry the 4 trigger waveform outputs in serial)
    • 2 bit wide channel-number signal (to specify which of the 4 channels each datum belongs to)
    • 1 bit wide valid signal
    • 1 bit wide start-of-packet signal
    • 1 bit wide end-of-packet signal
    • 2 bit wide error signal (which is ignored)
  • Packets will be sent at a rate of 39.0625 kHz, in lockstep with the input packets, with some latency which we will measure during testing of this module.
  • Note that the outputs from all 4 submodules are collected into a single 4-channel stream before they are passed to the Threshold Logic (ThL) module. The 4 submodule outputs are sent as a single packet to the ThL module, with each ThL submodule pulling its assigned data from the stream.

For an FIR filter, each value of the output sequence is a weighted sum of the most recent 1024 input values in time: \begin{aligned} \text{output}[n] & = b_{0} \cdot \text{input}[n] + b_{1} \cdot \text{input}[n-1] + \cdots + b_{1023} \cdot \text{input}[n-1023] \\ & = \sum_{i=0}^{1023} b_{i} \cdot \text{input}[n-i]\text{, where} \end{aligned}

• $i= 0, 1, 2, \cdots, 1023$ (indexes the most recent 1024 inputs from Linear Combination module)
• $b_{i}$ is the $i$'th coefficient
• $\text{input}[n-i]$ is the $i$'th most recent input in time stored in internal registers (e.g., $ \text{input}[n] $ is the most recent input, $ \text{input}[n-1] $ is the previous input)

This module is implemented as an Altera IP Core (FIR Compiler II), which requires certain parameters to be set at design time in order to specify the exact functionality that is needed from a fairly general-purpose piece of code. The list of parameters and the values we use are given later in this document (FIR II IP Core parameters).

Step-by-step:

This description is at a very high level because we are not implementing the FIR module ourselves. Instead, we are using the FIR Compiler II IP Core from Altera. Since it is closed source, we can only describe in general terms what is done. To be completely explicit, we do not need to write any code for the FIR module -- all of the functionality described on this page, including all of the steps listed below, is handled completely by the Altera FIR Compiler II IP Core.

1. Wait for an input packet to arrive from the LC modules
2. Dispatch each of the input data to the appropriate FIR submodule: input from LC 1 goes to FIR 1, LC 2 to FIR 2, etc.
3. Store the 1024 most recent input values to each submodule -- when each input is received, discard the oldest stored input and store the new input.
4. Multiply each of the 1024 stored input values $\text{input}[n-i]$ by the corresponding coefficient $b_{i}$
5. Sum the 1024 weighted values $b_{i} \cdot \text{input}[n-i]$
6. Send the sum as an $\text{output}[n]$
7. Return to step 1
8. The output of each FIR module is sent with the other three FIR modules in a single Avalon-ST packet, where we send the outputs for FIR1 first, then FIR2, FIR3 and FIR4 respectively using the same operations as described in the step 4 of LC module here.

Reset Signal:

• Resynchronize the Avalon-ST interfaces (Note that a reset does NOT clear out the most recent 1024 inputs, so the output may not be useful for 1024 timesteps after a reset).

• Go back to Step 1 of the detailed description.

• FIR Compiler II implements the four FIR filters in such a way that they share hardware resources such as multiplier blocks, thus conserving FPGA resource usage. This sharing enforces the use of multi-channel packetized Avalon-ST streams at both the input and the output.

• See here for the overall testing plan.
• See here for the testing plan for this module.