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Synchronizer

(Firmware coder: TBD)

Structure

The Synchronizer module aligns all 16 detector data inputs in time. This allows us to ensure that all the data from a single time step is passed through the trigger system together, at the rate produced by the Downsample Filter (DF) module, 39.0625 kHz. The inputs are received from 5 separate streaming inputs, one from each of the DF modules. The output is the fully aligned inputs and is sent to the Linear Combination (LC) modules as a single packet of 16 samples (12 phonon and 4 charge). Note that there are 4 LC modules; each gets an identical copy of the Synchronizer output.

Data Inputs There are 5 separate streaming inputs, one from each of the DF modules:
  • The 5 inputs contain the following information:
    • phonon channels 1-4
    • phonon channels 5-8
    • phonon channels 9-12
    • charge channels 1-2
    • charge channels 3-4
  • The inputs are formatted as 5 seperate mutiple-channel packetized Avalon-ST streams.
    • Each input stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
      • Data signal:
        • 26 bit wide data signal for each phonon input (which is used to carry the 4 words per stream in serial, 3 phonon streams total)
        • 34 bit wide data signal for each charge input (which is used to carry the 2 words per stream in serial, 2 charge streams total)
      • Channel-number signal:
        • 2 bit wide channel-number signal for each phonon input (to specify which of the 4 channels each datum belongs to)
        • 1 bit wide channel-number signal for each charge input (to specify which of the 2 channels each datum belongs to)
      • 1 bit wide valid signal
      • 1 bit wide ready signal, used for "backpressure", actually an output bit read by the data source (DF module) to indicate when we're ready to accept data -- always set to TRUE
      • 1 bit wide start-of-packet signal
      • 1 bit wide end-of-packet signal
      • 2 bit wide error signal (which is ignored)
    • Packets will be received at a rate of 39.0625 kHz.
    • Since each input carries multiple channels, exactly one datum from each constituent channel will be received in series as a single Avalon-ST packet.
    • Note that this module only deals with aligning the digital signals. We assume that any analog delays (such as due to variation in cable lengths) have already been handled.
Configuration and Control Inputs
  • 100 MHz clock input
  • 1 reset input
Output There is 1 streaming output, which goes to the LC module.
  • The output contains the following information:
    • phonon channels 1-12
    • charge channels 1-4
  • The output is formatted as a 16-channel packetized Avalon-ST stream.
    • The output stream includes the following signals (see table 5-1 of the Avalon-ST specification for detailed descriptions of the signal roles):
      • 34 bit wide data signal (which is used to carry the 16 outputs in serial)
      • 4 bit wide channel-number signal (to specify which of the 16 channels each datum belongs to)
      • 1 bit wide valid signal
      • 1 bit wide start-of-packet signal
      • 1 bit wide end-of-packet signal
    • Packets will be sent at a rate of 39.0625 kHz.
    • Note that each phonon channel and each charge channel is carried on its own Avalon-ST channel, and we assume an order in this description of all the phonon channels first (0-11) and then the charge channels (12-15). That is, when sending a sample from phonon channel 1, the Avalon-ST channel number bits will be set to 0000. When sending a sample from phonon channel 12, the Avalon-ST channel number bits will be set by the Synchronizer module to 1011. When sending a sample from charge channel 1, the Avalon-ST channel number bits will be set to 1100. When sending a sample from charge channel 4, the Avalon-ST channel number bits will be set to 1111. That is, phonon channels 1-12 are sent on Avalon-ST channels 0-11 respectively, and charge channels 1-4 are sent on Avalon-ST channels 12-15 respectively.
    • The charge samples use all 34 data bits, but the phonon samples use only 26, so they are zero-padded. For phonon samples, the 8 most-significant data bits are set to all zeros, and the 26 least-significant data bits carry the phonon sample data.
    • Note that the input includes two error bits, which are produced by the Downsample Filter (DF) module because it is implemented as an Altera CIC Filter IP Core. However, these bits are not used, so the output does not include any error bits.
Internal Registers

This module requires some information to be retained from one time step to the next. It will be stored in internal registers, which are not visible or accessible from outside the module. They are mentioned and named here in order to simplify the detailed description of the module's functionality given below.

  • 5 input-status registers: 1 bit each
    (These 5 bits indicate whether a input packet has arrived on each of the 5 input streams since the last time we sent an output packet.)
  • 16 input registers: 26 bits (phonon) or 34 bits (charge) each
    (These registers store the input data as it arrives, so that we can send all the input data in a single output packet once it has all arrived.)
Functionality Brief functional description:

This module both multiplexes the 5 input streams together and aligns them in time. The alignment is important because the inputs may not arrive at exactly the same time. This module addresses this by the virtue of the fact that an output packet is only sent when all the inputs have arrived (while this can create a latency, this does not affect the trigger functionality). Thus, each output packet contains 16 contemporaneous samples (one from each of the 12 phonon and 4 charge channels). Note that this module is the only module that has to perform this synchronization -- it is not needed in the other modules, because synchronicity is maintained downstream by grouping contemporaneous data together in Avalon-ST packets.

Note that this module only deals with aligning the digital signals. We assume that any analog delays (such as due to variation in cable lengths) have already been handled.

More detailed description (including data transfer information):

Step-by-step:

For each of the five input streams:
  1. Wait for an input packet to arrive from the DF Module
  2. When an input packet arrives, store each datum into its corresponding input register
  3. When the input packet is complete, set the input-status bit corresponding to this input stream
On every rising clock edge, check the five input-status bits:
  • If any of the input-status bits are 0, do nothing
  • If all of the input-status bits are 1, then send an output packet (which takes a total of 17 clock cycles):
    1. Set the 34 data bits to represent phonon channel 1, with the most-significant bits filled with zeros to pad the 26 phonon-sample bits out to 34 bits. Concurrently, set the 4 channel-number bits to 0000, set the valid bit, and set the start-of-packet bit.
    2. Set the 34 data bits to represent phonon channel 2, zero padded again. Concurrently, set the 4 channel-number bits to 0001, and unset the start-of-packet bit.
    3. Set the 34 data bits to represent phonon channel 3, including zero padding. Concurrently, set the 4 channel-number bits to 0010.
    4. Set the 34 data bits to represent phonon channel 4, including zero padding. Concurrently, set the 4 channel-number bits to 0011, and unset the input-status bit for the first phonon input stream
    5. Set the 34 data bits to represent phonon channel 5, including zero padding. Concurrently, set the 4 channel-number bits to 0100.
    6. Set the 34 data bits to represent phonon channel 6, including zero padding. Concurrently, set the 4 channel-number bits to 0101.
    7. Set the 34 data bits to represent phonon channel 7, including zero padding. Concurrently, set the 4 channel-number bits to 0110.
    8. Set the 34 data bits to represent phonon channel 8, including zero padding. Concurrently, set the 4 channel-number bits to 0111, and unset the input-status bit for the second phonon input stream
    9. Set the 34 data bits to represent phonon channel 9, including zero padding. Concurrently, set the 4 channel-number bits to 1000.
    10. Set the 34 data bits to represent phonon channel 10, including zero padding. Concurrently, set the 4 channel-number bits to 1001.
    11. Set the 34 data bits to represent phonon channel 11, including zero padding. Concurrently, set the 4 channel-number bits to 1010.
    12. Set the 34 data bits to represent phonon channel 12, including zero padding. Concurrently, set the 4 channel-number bits to 1011, and unset the input-status bit for the third phonon input stream
    13. Set the 34 data bits to represent charge channel 1 (no zero padding needed). Concurrently, set the 4 channel-number bits to 1100.
    14. Set the 34 data bits to represent charge channel 2 (no zero padding needed). Concurrently, set the 4 channel-number bits to 1101, and unset the input-status bit for the first charge input stream
    15. Set the 34 data bits to represent charge channel 3 (no zero padding needed). Concurrently, set the 4 channel-number bits to 1110.
    16. Set the 34 data bits to represent charge channel 4 (no zero padding needed). Concurrently, set the 4 channel-number bits to 1111, and unset the input-status bit for the second charge input stream, and set the end-of-packet bit.
    17. Unset the valid bit, and unset the end-of-packet bit.

Reset Signal:

When the reset signal is asserted,
  • Set the internal input-status registers to zero
  • Set the internal input registers to zero
When the reset signal is deasserted,
  • Go back to normal running
Testing Plan
  • See here for the overall testing plan.
  • See here for the testing plan for this module.