External Triggers and Vetos (ETV)

The inputs are derived from the external connectors on the DCRC, which takes in signals from the signal distribution unit (SDU). The input can be one of the following three:

• An external trigger input
• A start veto input
• A stop veto input

Note that the data format is not yet specified. Input is needed from Sten about the format and meaning of the SDU signals and how they can be used in the FPGA.

The input signals will be something simple, along the lines of a bit that is high on a rising clock edge, plus a couple of bits to indicate the type of input (external trigger, start veto, or stop veto). The final specification of the inputs will not be available until Sten has had a chance to get the design of the SDU at least closer to finished.

• 100 MHz clock input
• 1 reset input
• Current timestamp: 32 bits
  (This is a counter that is incremented by the DCRC every time a phonon ADC sample is stored into memory. It is not a part of the trigger firmware, and is instead computed by the main DCRC firmware and provided to the trigger firmware as well as to other parts of the main DCRC firmware. It is set to zero at the beginning of a series, and so it records the number of phonon samples recorded since the series start. It will roll over to zero about every 2 hours, which is more than long enough to avoid any ambiguity for the MIDAS front-end. The same counter is used by the Random Trigger and Peak Search modules to provide trigger timestamps.)

• The output is a set of trigger primitives and comprises the following information:
  • Timestamp of the trigger or veto
  • A special code used to indicate the nature and source of the external trigger or veto
  • The trigger word, which for external triggers and vetos is all zeros
  • The trigger logic bits, which for external triggers and vetos is all ones
• The output is an Avalon-ST format stream.
• The output stream includes the following signals:
  • 72 data bits, broken down as follows, ordered from the most-significant bits to the least-significant bits:
    • 32 bits: timestamp
    • 16 bits: trigger/veto special code
    • 16 bits: all set to 0
    • 8 bits: all set to 1
  • 1 "valid" bit
• Each output produced by this module (or by the Random Trigger and Trigger Logic modules) produces a single entry in the FIFO.

The ETV module takes in input received from the external trigger sources and, depending on the input, produces one of three words to send to the L1 FIFO module.

Step-by-step:

1. Receive an input from the external connectors
2. Check the input:
   • If an external trigger input is received, send the following 72 bits as an output
     • 32 bit timestamp: current timestamp
     • 16 bits: a code (3 or greater) that indicates the source of the external trigger
     • 16 bits: all 0
     • 8 bits: all 1
   • If a start veto input is received, send the following 72 bits as an output
     • 32 bit timestamp: current timestamp
     • 16 bits: 1 (code indicating veto start)
     • 16 bits: all 0
     • 8 bits: all 1
   • If an end veto input is received, send the following 72 bits as an output
     • 32 bit timestamp: current timestamp
     • 16 bits: 2 (code indicating veto stop)
     • 16 bits: all 0
     • 8 bits: all 1
3. Return to step 1

Reset Signal:

• Do nothing, ignoring all input. There is no internal state to reset.

• Go back to Step 1